Friday, 20 November 2015
http://www.spiroprojects.com/final-year-projects.php?subcat_name=Final-Year-3D-Printing-Technology-Projects-in-chennai&sub_cat_id=563D PRINING TECHNOLOGY
Tuesday, 22 September 2015
The quest for Linux friendly embedded board makers
We used to keep a list of Linux friendly embedded board makers. When
this page was created in the mid 2000s, this page was easy to maintain.
Though more and more products were created with Linux, it was still
difficult to find good hardware platforms that were supported by Linux.
So, to help community members and system makers selecting hardware
for their embedded Linux projects, we compiled a first selection of
board makers that were meeting the below criteria:
Therefore, we added another prerequisite: at least one product supported (at least partially) in the official version of the corresponding Free Software operating system kernel. This was a rather strong requirement at first, but only such products bring a guarantee for long term community support, making it much easier to develop and maintain embedded systems. Compare this with hardware supporting only a very old and heavily patched Linux kernel, for example, which software can only be maintained by its original developers. This also reveals the ability of the hardware vendor to work with the community and share technical information with its users and developers.
Then, with the development of low-cost community boards, and chip manufacturers efforts to support their hardware in the mainline Linux kernel, the list again became difficult to maintain.
The next prerequisite we could add is the availability as Open-source hardware, allowing customers to modify the hardware according to their needs. Of course, hardware files should be available without registration.
However, rather than keeping our own list, the best is to contribute to Wikipedia, which has a dedicated page on Open-Source computing hardware. At least, all the boards we could find are listed there, after adding a few.
Don’t hesitate to post comments to this page to share information about hardware which could be worth adding to this Wikipedia page!
Anyway, the good news is that Linux and Open-Source friendly hardware is now easier and easier to find than it was about 10 years back. Just have a preference for hardware that is supported in the mainline Linux kernel sources, or at least from a maker with earlier products which are already supported. A
- Offering attractive and competitive products
- At least one product supported Free Software operating systems (such as Linux, eCos and NetBSD.
- At least one product meeting the above requirements, with a public price (without having to register), and still available on the market.
- Specifications and documentation directly available on the website (no registration required). Engineers like to study their options on their own without having to share their contact details with salespeople who would then chase them through their entire life, trying to sell inappropriate products to them.
- Website with an English version.
Therefore, we added another prerequisite: at least one product supported (at least partially) in the official version of the corresponding Free Software operating system kernel. This was a rather strong requirement at first, but only such products bring a guarantee for long term community support, making it much easier to develop and maintain embedded systems. Compare this with hardware supporting only a very old and heavily patched Linux kernel, for example, which software can only be maintained by its original developers. This also reveals the ability of the hardware vendor to work with the community and share technical information with its users and developers.
Then, with the development of low-cost community boards, and chip manufacturers efforts to support their hardware in the mainline Linux kernel, the list again became difficult to maintain.
The next prerequisite we could add is the availability as Open-source hardware, allowing customers to modify the hardware according to their needs. Of course, hardware files should be available without registration.
However, rather than keeping our own list, the best is to contribute to Wikipedia, which has a dedicated page on Open-Source computing hardware. At least, all the boards we could find are listed there, after adding a few.
Don’t hesitate to post comments to this page to share information about hardware which could be worth adding to this Wikipedia page!
Anyway, the good news is that Linux and Open-Source friendly hardware is now easier and easier to find than it was about 10 years back. Just have a preference for hardware that is supported in the mainline Linux kernel sources, or at least from a maker with earlier products which are already supported. A
git grep -i command in the sources will help.Placement of Clock Gating Cells using VLSI
Clock Gating Cells are indispensable components to save dynamic power. However, the backend design engineers must be prudent while placing them. In this post, I'll talk about the trade-off between timing and power that underlies the placement of clock gating cells.
Consider that your SoC has two IPs, and a single clock source. These two IPs are synchronous, and might work independently (i.e. without any interaction with the other IP) in some use-case of the chip. This entails the need of two clock gating cells. Now the question arises: where to place these clock gating cells.
- Near the sink, i.e. the clock source, or
- Near the source, i.e. the respective IPs
Let's take up pros and cons of the two placement scenarios.
1.Clock Gating Cells placed near the source: As shown in the
figure, placing the clock gating cells near the clock source, can the
increase the uncommon clock path (shown in yellow).
Recall from the post: Common Path Pessimism that while doing timing analysis, the effect of OCV derates come into picture for the uncommon clock path because the clock tree buffers in the uncommon path can behave differently and hence an STA engineer needs to take into account that extra uncertainty or pessimism while doing timing analysis. Such a scenario is therefore hostile to the timing engineers. However, from power perspective this scheme is quite favorable. Since as soon as the clock gate is turned "Off", all the clock buffers in the fanout of that clock gate are also "off" or in other words, they do not toggle and hence do not dissipate dynamic power. Like any engineering problem, there exists a trade-off between two conflicting factors, and designers often need to prioritize.
2. Clock Gating Cells placed near the sink: While this scenario, with greater common path as compared to the first scenario and hence making the timing easier to met, is not friendly from the power perspective.
All the clock tree buffers in the common clock path (shown tin red) lie before the clock gate and hence would always be "on" and keep on toggling at the clock frequency, thereby dissipating dynamic power.
Solution:
The pertinence of a solution is dictated on many factors. Permissible clock latencies, power dissipation specifications, timing closure challenges and also the use-case.
Let's say we had a requirement that IP 2 will function if and only if IP 1 is on. In this case we could have placed the clock gates in series like this:
By having the two clock gates in series, we would save the dynamic power of all the clock tree buffers in the fanout of first clock gate. Moreover, the uncommon path is significantly less as compared to the scenario 1.
Again note that this solution would not work if we had the use-case where IP 1 could be "off", while IP 2 still "on".
Common Path Pessimism in VLSI
Common Path Pessimism is a common source of some extra pessimism in timing analysis. Before we delve further into this, note that pessimism can be of two types:Intended and Unwanted. Intended pessimism could be like adding some extra uncertainty for clock skew before CTS stage, or some uncertainty for noise before SI (Signal Integrity) analysis. It is often prudent to have this pessimism taken upfront in your design because it will avoid any surprises when you move from one stage to another.
Having said that, which category do you reckon should Common Path Pessimism fall? Let's define it first and then we'll take a look at it objectively.
When any pair of launching and capturing flop have a some portion of clock path as common, the difference between the max and min delay of that common clock segment is referred to as Common Path Pessimism. We discussed the rationale behind the use of timing derates briefly in the post: OCV vs PVT. Note that the entire timing analysis revolves around this intended pessimism where the basic aim is to make the timing paths more critical to avoid seeing any surprises in the silicon. EDA tools, however, themselves have quite a fair amount of pessimism, it is always prudent for the STA engineers to augment some uncertainty/pessimism in their timing analysis.
Convince yourself that:
So, while doing setup analysis, the clock tree buffers in the launching path would be derated by +5% and in the capturing path would be derated by -5&. The data path would be derated by +5%.
While doing hold analysis, it would be the opposite. The clock tree buffers in the launching path would be derated by -5% and in the capturing path would be derated by +5&. The data path would be derated by -5%.
How would the situation change when there's a common clock path? Let's take a look.
Ideally speaking, for setup analysis, we would like to take the +5% derated value of the delay of these buffers while considering launching path and -5% derated value while considering the capture path. However, here lies the catch! How can the same buffer or set of buffers be derated differently for launch and capture? Recall from the definition of OCV that it is the intra-chip variation in PVT that STA engineers consider them in the first place.
However, now these buffers, they are in the same location. So at a time they would behave in a similar manner. It does not make sense to consider different delays for same buffers. And this is the origin of common path pessimism and in usually unwanted. What we can do is (or rather what EDA tools tend to do is), do the calculation considering common path to be non-existent. And in the slack, add the double derated value of the common buffers, which would be 10% of the three common buffers in this case. This is referred to as Common Path Pessimism Removal.
Convince yourself that:
- Setup check would be most critical when clock reaches the launching flop late and capturing flop early; and the data path takes more delay.
- Hold check would be most critical when clock reaches the launching flop early, capturing flop late and data path takes less delay.
Consider the following example with no common clock path and note that we have just applied the above principle to add pessimism in timing analysis.
While doing hold analysis, it would be the opposite. The clock tree buffers in the launching path would be derated by -5% and in the capturing path would be derated by +5&. The data path would be derated by -5%.
How would the situation change when there's a common clock path? Let's take a look.
However, now these buffers, they are in the same location. So at a time they would behave in a similar manner. It does not make sense to consider different delays for same buffers. And this is the origin of common path pessimism and in usually unwanted. What we can do is (or rather what EDA tools tend to do is), do the calculation considering common path to be non-existent. And in the slack, add the double derated value of the common buffers, which would be 10% of the three common buffers in this case. This is referred to as Common Path Pessimism Removal.
Friday, 11 September 2015
Saturday, 5 September 2015
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ITMA01 Power generation by using hydraulic brakes system in automobiles
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ITMA04 Automatic differential locking system
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23 ITMA08 Automatic braking and bumper system for automobiles
24 ITMA09 Modification of exhaust system of 2-wheeler for emission
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26 ITMA11 Power transmission through timing belt in 2-wheeler
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31 ITMF01 Fabrication of energy regenerative bi-cycle using fly wheel
32 ITMF02 Fabrication of roll-to-roll fluidic assembly
33 ITMF03 Development of non-conventional portable abrasive jet machine
34 ITMF04 Coconut tree climbing and cutting machine
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PROJECT TITLES
ITMT01 - Fabrication and testing of refrigeration using engine waste heat
ITMT02 - Cyclone separator with blower
ITMT03 - Fabrication of miniature boiler
ITMT04 - Fabrication of plate freezer
ITMT05 - Waste chill recovery heat ex changer
ITMT06 - Industrial boiler flame adjustment system
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ITMT09 - Fabrication of auto air conditioner generator utilizing exhaust waste energy
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medium and agitator
ITMT11 - Solar aided portable vacuum desalination system
ITMT12 - Testing and validation of thermo-electric coolers
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